The present invention relates generally to computers, and more particularly to techniques for efficient pipeline control thereof.
A single cycle implementation of a complex instruction set computer (CISC) architecture requires a deep pipeline. When combined with the complex privilege and protection checks and powerful memory management systems directly supported by a CISC architecture, conventional pipeline control techniques become very complicated. In current technology, the pipeline has to include the effects of multiple chip boundary crossings. In attempting to eliminate as many of these crossings as possible, high levels of VLSI integration are chosen. With a relatively small number of devices in the system, there aren't enough signal pins to run dedicated buses for every purpose. This means that the buses must be used for multiple purposes, greatly complicating the process of designing a centralized control and scheduling mechanism.